1. Technical Field
The present invention relates to a semiconductor structure comprising a buried oxide layer and a plurality of trench isolation structures, and to a method for forming the semiconductor structure.
2. Related Art
A semiconductor structure typically comprises semiconductor devices, such as transistors, which need to be electrically isolated from other semiconductor devices. Various isolation structures, such as a buried oxide layer (xe2x80x9cBOXxe2x80x9d) or a trench isolation structure (xe2x80x9ctrenchxe2x80x9d), have been used in semiconductor structures to accomplish such isolation. Viewing the vertical direction as into the depth, or thickness, of a given substrate and the horizontal direction as being parallel to a top surface of the substrate, a BOX is a horizontally oriented layer that provides insulative separation between semiconductor devices at different vertical locations, while a trench such as a shallow trench isolation is a vertically oriented structure that provides insulative separation between semiconductor devices at different horizontal locations.
A BOX comprises an oxide of an intrinsic semiconductor such as crystalline silicon and may be formed in various ways, such as by using oxygen ion implantation techniques which are known by those skilled in the art. A particular manner of using ion implantation to form a BOX of varying depth comprises: optionally xe2x80x9cgrowingxe2x80x9d a thin (e.g., 80 angstroms) pad oxide (SiO2) layer on the top surface by exposing the top surface to oxygen at high temperature, depositing a thicker (e.g., 3000 angstroms) layer of silicon nitride (Si3N4) over the pad oxide, patterning the top surface with photoresist, exposing the top surface to ultraviolet radiation, etching the unexposed silicon nitride, implanting oxygen into the substrate, annealing, stripping away the silicon nitride layer, and stripping away the pad oxide layer. The pad oxide is a buffer which reduces stresses resulting from crystal mismatch between the silicon nitride layer and the substrate. The forming of the silicon nitride layer may be accomplished by any suitable technique, such as by chemical vapor deposition. The etching of silicon nitride determines the horizontal distribution of silicon nitride thickness on the top surface and the silicon nitride thickness controls the depth of oxygen implantation. Thus, selective etching of the silicon nitride layer enables a BOX of varying depth to be formed. The oxygen implantation is generally performed at high energy density such as at 1018/cm2 at 200 keV as disclosed in U.S. Pat. No. 5,364,800 (Joyner, Jun. 24, 1993, page 1, lines 40-42). The annealing is typically performed at high temperature (e.g., 1300xc2x0 F. for 6 hours as disclosed in U.S. Pat. No. 5,364,800, page 1, lines 43-46) to cause SiO2 formation and repair crystal damage. Another method of forming a BOX of varying depth comprises directing an oxygen ion beam through a silicon dioxide screen of varying thickness and then into the depth of the substrate (see U.S. Pat. No. 5,364,800).
A trench is a vertical cavity from the top surface into the depth of the substrate, wherein electrically insulative material is placed within the cavity. A trench may be formed by techniques known by those skilled in the art. U.S. Pat. No. 5,536,675 (Bohr, Aug. 7, 1995) discloses such a technique comprising: growing a pad oxide (SiO2) layer on the top surface of the substrate, depositing of a layer of silicon nitride (Si3N4) over the pad oxide, patterning the top surface with photoresist, exposing the top surface to ultraviolet radiation, etching through the unexposed silicon nitride and continuing to etch through the pad oxide and the underneath substrate to a desired depth to form the trench, optionally growing an oxide lining on the interior surfaces of the trench to passify the interior surfaces which may have been damaged during etching of the substrate, inserting insulative material into the trench to above the top surface, and optionally polishing to remove insulative material from above the top surface. The etching of the substrate may be accomplished by using a plasma comprising HBr and NF3, or any other suitable etching chemical material such as SiF4. The etching may be performed isotropically or anisotropically for generating vertical and/or sloped sidewalls. Any suitable insulative material, such as silicon dioxide, silicon nitride, or spin-on glass, may be used. The insulative material is distributed within the trench so as to provide electrical insulation between semiconductor regions respectively bordering the two sides of the trench that project into the substrate from the top surface.
U.S. Pat. No. 5,536,675 also discloses how the preceding process may be modified to form a T-shaped trench comprising two contiguous segments, wherein the top segment is wider than the bottom segment. Following formation of the first cavity as described above, the substrate is patterned with a photoresist and exposed to ultraviolet radiation so as to leave the bottom of the first cavity unprotected from subsequent etching. Then a second cavity segment is formed by etching deeper into the substrate from the bottom of the first cavity. U.S. Pat. No. 5,536,675 also discloses how the preceding processes may be modified to generate a shallow trench and a T-shaped deep trench having a narrow cavity segment underneath a wider upper segment, wherein the shallow trench and the wider upper segment of the T-shaped trench may be etched concurrently by covering the substrate with a suitable photoresist pattern prior to etching. A variety of methods of using photoresist patterning, exposure, and etching may be exploited to form a plurality of trenches concurrently. For example, a first cavity in a first location may be formed in isolation, followed by photoresist patterning, exposure, and etching so as to form a T-shaped trench in the first location while simultaneously forming an unsegmented trench in a second location.
The prior art does not disclose semiconductor structures having isolation characteristics that permit particular combinations of semiconductor devices, such as a fully depleted and partially depleted field effect transistors (FETs), to be formed on the same substrate.
All heretofore mentioned prior art is hereby incorporated by reference.
The present invention provides semiconductor structures, and associated methods of fabrication, having isolation characteristics that permit particular combinations of semiconductor devices, such as a fully depleted and partially depleted FETs, to be formed on the same substrate. A semiconductor structure of the present invention comprises: a substrate having a top surface, a continuous BOX of semiconductor oxide, and a plurality of trenches embedded within the substrate. The depth of the BOX may vary spatially in any manner that maintains the continuity of the BOX. Each trench comprises a point on the top surface and extends into the substrate as a vertical array of one or more contiguous segments. Each trench comprises electrically insulative matter so as to facilitate electrical separation between devices.
An embodiment of the present invention consists of a semiconductor structure comprising: a substrate having a top surface, a continuous depth-varying BOX, a first trench, and a second trench, wherein both the first trench and the second trench are positioned between the top surface and the BOX. The first trench and the second trench may each penetrate the substrate to the same depth or to different depths. The first trench and the second trench may each touch or not touch the BOX. The first trench and the second trench may each have one segment or a plurality of segments. Regions within the substrate which are electrically separated by the insulative barrier of the first trench, or of the second trench, may comprise a semiconductor device.
Another embodiment of the present invention provides a semiconductor structure, and associated methods of fabrication, comprising a substrate having a top surface, a continuous depth-varying BOX, a first trench positioned between the top surface and the BOX, and an external trench. The external trench is external to a first region between the BOX and the first surface. The external trench borders a side of the first region and touches an end surface of the BOX such that the external trench electrically isolates the first region from a second region within the substrate.
The present invention additionally provides a semiconductor structure comprising:
a substrate having a first surface;
a continuous buried oxide layer within the substrate, wherein a first portion of the buried oxide layer is disposed at a first depth relative to a point on the first surface, and wherein a second portion of the buried oxide layer is disposed at a second depth relative to the point on the first surface;
a first semiconductor region between the first surface and the first depth of the buried oxide layer, wherein the first semiconductor region touches the first surface and touches the buried oxide layer at the first depth;
a second semiconductor region between the first surface and the second depth of the buried oxide layer, wherein the second semiconductor region touches the first surface and does not touch the buried oxide layer;
a gate structure on the top surface, laterally between the first semiconductor region and the second semiconductor region; and
a third semiconductor region between the first surface and the buried oxide layer, wherein the third semiconductor region is continuously distributed between the first surface and the buried oxide layer, and wherein the third semiconductor region touches the buried oxide layer at the second depth, the first semiconductor region, the second semiconductor region, and the gate structure.
The BOX and the trenches for the semiconductor structures of the present invention may be formed by methods known to those skilled in the art as discussed previously. For each circuit, the BOX is formed before the trenches are formed. Each trench of a plurality of trenches may be formed in any order and portions of two or more trenches may be formed simultaneously by suitable photoresist patterning, exposure, and etching.
It is an object of the present invention to provide silicon-on-insulator (SOI) devices with both fully depleted and partially depleted elements on a common substrate.
It is an object of the present invention to provide SOI circuit elements for both digital and analog application on a common wafer.
It is an object of the present invention to provide SOI circuit elements for usage as electrostatic discharge (ESD) protection networks.
It is an object of the present invention to provide an improved resistor element in SOI technology.
It is an object of the present invention to an asymmetric structure to exist with a dual-step BOX.
It is an object of the present invention to allow low and high junction capacitance regions to exist with a dual-depth BOX.
It is an object of the present invention to allow an asymmetric gated lateral diode structure to exist with a dual-depth BOX.
It is an object of the present invention to permit a gated lateral diode and a vertical diode to coexist with a dual-depth BOX.
By having a BOX exist at different substrate depths and utilizing trenches having different depths of penetration, the present invention offers the following advantages. Combinations of many different semiconductor devices may coexist on the same substrate, including combinations of FETs, bipolar transistors, decoupling capacitors, diodes, gated diodes, resistors, and bulk semiconductor devices. Deep devices and shallow devices may coexist on the same substrate. Fully depleted and partially depleted FETs may coexist on the same substrate. Low capacitance MOFSETs and high capacitance MOFSETs may coexist on the same substrate. MOFSETS with low and high body electrical resistance may coexist on the same substrate. Bipolar devices and CMOS devices may coexist on the same substrate. A low-resistance shunt may be placed, without depth limitation, between an N-well resistor and the BOX while being electrically separated by a trench from another device located at a more shallow depth. Increased flexibility is afforded for dissipating heat from devices that protect chip circuits from electrostatic discharge (ESD), because a narrow space between a trench and the BOX provides a relatively low thermal resistance path for dissipating heat.